Field of the Invention
The present invention is related to manufacturing Integrated Circuits (ICs) with logic cells and more particularly to forming contacts from logic chip wiring layers to fin field effect transistor (finFET).
Background Description
A typical integrated circuit (IC) chip includes several stacked or sequentially formed layers of shapes of various materials, e.g., semiconductors, insulators and metals. For example, the intersection of two rectangles, a gate layer rectangle on a rectangular channel layer forms a simple Field Effect Transistor (FET). In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, the layers are formed on a wafer to form pairs of opposite type devices, N-type FETs (NFETs) and P-type FETs (PFETs), on a surface of the wafer, e.g., a silicon surface layer of a Silicon On Insulator (SOI) wafer or a bulk semiconductor wafer. One or more FET pairs may be connected together into logic blocks, memory cells and more complex circuits.
Each layer of shapes, also known as a mask level or mask layer, may be created or printed optically through well-known photolithographic exposure and development steps. Typical such patterning steps may include, for example, etching, dopant implanting and material deposition. A mask for each layer may be stacked or overlaid precisely on a prior layer and patterned from the mask to form the shapes that define devices (e.g., FETs)) and connect the devices into circuits. Usually, unless steps are taken to avoid it, each layer forms an irregular surface on another irregular surface, which complicates forming features that reflect the original layout or design.
IC chip density and performance are primary semiconductor technology development goals. Increased chip density (the average density of circuit transistors on a chip) and chip die size has increased the number of transistors packed on a single chip. Typically, chip density has been achieved by shrinking features sizes to pack more transistors in the same area. Chip density also has been increased by forming FETs vertically on narrow semiconductor surface ridges or fins. Minimum feature sized lines of semiconductor material (fins) are formed on the surface of a bulk wafer or from the surface layer of an SOI wafer. Gates on the fins form tightly packed vertical FETs, known as finFETs. The surface above these ridge type features (narrow metal gates orthogonally formed on minimum sized fins) can be very irregular.
A typical logic array technology, e.g., standard cell or brick wall, includes a library of logic blocks or circuits that may range from simple elemental logic (e.g., inverters and NAND/NOR gates) to more complex functions, such as n-bit registers, adders and multipliers. Wiring from essentially straight line shapes on a wiring layer (above the gate layer) connects array cell FETs (e.g., finFETs) into library logic blocks. Normally, a logic array chip includes additional wiring layers for global wiring that connects the logic blocks together into higher order, more complex circuits, and connects the higher order circuits together into chip functions, and off chip.
Typically, these additional wiring layers alternate wiring direction, e.g., a horizontally (x) oriented wiring layer beneath a vertically oriented (y) wiring layer beneath another horizontally oriented wiring layer and so on. Thus, wires on each layer may be oriented in a single direction with direction changes made through interlevel vias connecting wires on one layer to wires above or below that layer. Wires deviating from the normal layer direction cross other wiring channels, blocking those channels and increasing congestion. The more logic a chip includes, the more likely severe routing congestion becomes. A typical logic chip, for example, may use all available space on one or more wiring layers. Thus essentially, chip wiring congestion limits logic chips circuit/function density.
In what is known as physical design, various optical and resist patterning tools convert a layout into layout data, the layout data into masks used for printing chip layers. These patterning tools and materials have associated non-linearities that cause shape interactions, commonly known as optical effects. Thus, it is common to lose design shape fidelity from design to printing, both from the tools and from other adjacent shapes in the vicinity. For example, straight lines (e.g., wires) tend to print such that the ends pull back in what is known as “line-end shortening” effects. Rectangular corners, both inside and outside, print and etch rounded in what is known as “corner rounding” effects.
FinFET logic cell libraries may use what are known as in-line gate pickups. In-line gate pickups are logic block connecting wires on the lowest wiring layer in channels that are superimposed on (in-line with) gates they connect. While in-line pickups connect to finFET gates, connecting externally requires bi-directional metal wiring (x and y) for interlevel vias, jogging from the level wiring direction to connect to subsequent wiring layers. Bi-directional metal wiring incurs tip-to-side (T2S) printability issues that reduce chip yield. T2S printability issues arise from the coincidence of line-end shortening (tip/end pull-back) and corner rounding at inside corners. T2S printability trades off shorts for opens and vice versa, e.g., from line-ends shorting to the sides of adjacent lines and, line opens from biasing lines to maintain separation with adjacent ends.
When T2S issues are severe enough FinFET logic cell libraries use what are known as offset drops that allow stacking vias on gate contacts to maintain unidirectional wiring layers. Offset drops are, essentially, elongated rectangular contacts with one side over a finFET gate and the other connecting a wire and/or a via, more or less between gates. However, because offset drops effectively occupy double wide channels, they tend to push the limit on gate to contact spacing with shorts to adjacent gates occurring more frequently. Gate to contact shorts also reduce chip yield. Regardless of the cause, reduced chip yield increases production cost.
Thus, there is a need for improved yield from dense logic chip block wiring, and more particularly, for logic chip block wiring drops that do not require intra-block bidirectional wiring within gate to contact spacing limits.